Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
IEEE Design & Test
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Journal of Electronic Testing: Theory and Applications
Resistive bridging fault simulation of industrial circuits
Proceedings of the conference on Design, automation and test in Europe
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Built-in sensor for signal integrity faults in digital interconnect signals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new automatic pattern generation methodology to stimulate the maximum power supply noise in deep submicron CMOS circuits. Our ATPG-based approach first generates the required patterns to cover 0 驴 1 and 1 驴 0 transitions on each node of internal circuitry. Then, we apply a greedy heuristic to find the worst-case (maximum) instantaneous current and stimulate maximum switching activity inside the circuit. The quality of these patterns were verified by SPICE simulation. Experimental results show that the pattern pair generated by this approach produces a tight lower bound on the maximum power supply noise.