Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
High speed CMOS design styles
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
High-Speed Digital Circuits
DSP-Based Testing of Analog and Mixed-Signal Circuits
DSP-Based Testing of Analog and Mixed-Signal Circuits
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
IEEE Design & Test
Testing interconnects for noise and skew in gigahertz SoCs
Proceedings of the IEEE International Test Conference 2001
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
CMOS Electronics: How It Works, How It Fails
CMOS Electronics: How It Works, How It Fails
Signal Integrity Verification using High Speed Monitors
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Guest Editors' Introduction: Exploring Synergies for Design Verification
IEEE Design & Test
Pattern Generation and Estimation for Power Supply Noise Analysis
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Testing Skew and Logic Faults in SoC Interconnects
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Crosstalk noise control in an SoC physical design flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect-aware low-power high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.