CMOS Electronics: How It Works, How It Fails

Analysis of the impact of bus implemented EDCs on on-chip SSN

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Test set enrichment using a probabilistic fault model and the theory of output deviations

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Stochastic interconnect layout sensitivity model

Proceedings of the 2007 international workshop on System level interconnect prediction

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs

Proceedings of the conference on Design, automation and test in Europe

A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects

Journal of Electronic Testing: Theory and Applications

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Architecture Design for Soft Errors

Architecture Design for Soft Errors

Injecting various faults for the dependability validation of commercial microcontrollers

ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing

Built-in sensor for signal integrity faults in digital interconnect signals

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Multi-temperature testing for core-based system-on-chip

Proceedings of the Conference on Design, Automation and Test in Europe

Optimizing power and performance for reliable on-chip networks

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

Journal of Electronic Testing: Theory and Applications

Runtime asynchronous fault tolerance via speculation

Proceedings of the Tenth International Symposium on Code Generation and Optimization