Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics
Proceedings of the conference on Design, automation and test in Europe
CMOS Electronics: How It Works, How It Fails
CMOS Electronics: How It Works, How It Fails
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
Journal of Electronic Testing: Theory and Applications
An indirect current sensing technique for IDDQ and IDDT tests
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Fault detection in switched current circuits using built-in transient current sensors
Journal of Electronic Testing: Theory and Applications
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing)
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing)
IEEE Std 1500 Enables Modular SoC Testing
IEEE Design & Test
FGMOS Based Built-In Current Sensor for Low Supply Voltage Analog and Mixed-Signal Circuits Testing
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Experimental Characterization of CMOS Interconnect Open Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.