A practical current sensing technique for IDDQ testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip transient current monitor for testing of low-voltage CMOS IC
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A completey on-chip voltage regulation technique for low power digital circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Dynamic Power Supply Current Testing of CMOS SRAMs
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Improving bus test via IDDT and boundary scan
Proceedings of the 38th annual Design Automation Conference
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Built-in current sensor for IDDQ test
DBT '04 Proceedings of the 2004 IEEE International Workshop on Defect Based Testing
Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
An indirect current sensing technique for IDDQ and IDDT tests is proposed in this paper. This is accomplished by utilizing the pervasive on-chip voltage regulators and thus have little or no impact on CUT's design and its performance. We demonstrate that the proposed technique can be applied to both IDDQ and IDDT tests. Experiments were successfully conducted in SPICE simulations assuming the TSMC 0.18μm CMOS technology.