Identifying defects in deep-submicron CMOS ICs
IEEE Spectrum
IC test using the energy consumption ratio
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Improving Board and System Test: A Proposal to Integrate Boundary Scan and IDDQ
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Transient Power Supply Current Testing of Digital CMOS Circuits
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Digital Integrated Circuit Testing using Transient Signal Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Process-Aggravated Noise (PAN): New Validation and Test Problems
Proceedings of the IEEE International Test Conference on Test and Design Validity
Experiences with Implementation of IDDQ Test for Identification and Automotive Products
Proceedings of the IEEE International Test Conference
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits
Proceedings of the IEEE International Test Conference
Transient Power Supply Voltage (VDDT) Analysis for Detecting IC Defects
Proceedings of the IEEE International Test Conference
Test Strategy Sensitivity to Defect Parameters
Proceedings of the IEEE International Test Conference
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
iDD Pulse Response Testing of Analog and Digital CMOS Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Power Supply Transient Signal Integration Circuit
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An indirect current sensing technique for IDDQ and IDDT tests
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
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This paper presents a systematic test methodology targeting bus line interconnect defects using IDDT testing and Boundary Scan. Traditional test is unable to detect all possible defects, especially timing-related faults. Open and short defects on interconnects between embedded modules can be detected by IDDT testing. Boundary Scan can provide accessibility to internal buses. A statistical analysis is presented discussing the uncertain factors due to process variations and power fluctuation. The effectiveness of the proposed technique on shorts, opens or the other non stuck-at fault type defects is also illustrated.