Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Improving bus test via IDDT and boundary scan
Proceedings of the 38th annual Design Automation Conference
Signal integrity fault analysis using reduced-order modeling
Proceedings of the 39th annual Design Automation Conference
Crosstalk Minimization in Three-Layer HVH Channel Routing
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Proposal to Simplify Development of a Mixed-Signal Test Standard
Proceedings of the IEEE International Test Conference on Test and Design Validity
Early Capture for Boundary Scan Timing Measurements
Proceedings of the IEEE International Test Conference on Test and Design Validity
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Solving capture in switched two-node Ethernets by changing only one node
LCN '95 Proceedings of the 20th Annual IEEE Conference on Local Computer Networks
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs
Journal of Electronic Testing: Theory and Applications
Test generation for capacitance and inductance induced noise on interconnects in vlsi logic
Test generation for capacitance and inductance induced noise on interconnects in vlsi logic
Testing SoC interconnects for signal integrity using extended JTAG architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint-Driven Test Scheduling for NoC-Based Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing Network-on-Chip Communication Fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
Online traffic-aware fault detection for networks-on-chip
Journal of Parallel and Distributed Computing
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With advance in technology and working frequency reaching gigahertz, designing and testing interconnects have become an important issue. In this paper, we proposed a BIST-based boundary scan architecture to at-speed test of crosstalk faults for inter-switch communication links in network on chip. This architecture includes enhanced cells intended for MVT model test patterns generation and analysis test responses. One new instruction is used to control cells and TPG controller in the at-speed test mode in order to fully comply with conventional IEEE 1149.1 standard.