A new high-speed interconnect crosstalk fault model and compression for test space
WSEAS TRANSACTIONS on COMMUNICATIONS
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test pattern generation for crosstalk fault of high-speed interconnect
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
Journal of Electronic Testing: Theory and Applications
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
Online traffic-aware fault detection for networks-on-chip
Journal of Parallel and Distributed Computing
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As the technology is shrinking toward 50 nm and the workingfrequency is going into multi gigahertz range, the effect ofinterconnectson functionality and performance of system-on-chips isbecoming dominant. More specifically, distortion (integrity loss)of signals traveling on high-speed interconnects can no longer beignored. In this paper, we propose a new fault model, calledmultiple transition, and its corresponding test pattern generationmechanism. We also extend the conventional boundary scanarchitecture to allow testing signal integrity in SoCinterconnects. Our extended JTAG architecture collects and outputsthe integrity loss information using the enhanced observationcells. The architecture fully complies with the JTAG standard andcan be adopted by any SoC that is IEEE 1149.1 compliant.