Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Signal integrity fault analysis using reduced-order modeling
Proceedings of the 39th annual Design Automation Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Solving capture in switched two-node Ethernets by changing only one node
LCN '95 Proceedings of the 20th Annual IEEE Conference on Local Computer Networks
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
The Impact of NoC Reuse on the Testing of Core-based Systems
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Clocking strategies for networks-on-chip
Networks on chip
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
ICCD '03 Proceedings of the 21st International Conference on Computer Design
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
BIST for Network-on-Chip Interconnect Infrastructures
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs
Journal of Electronic Testing: Theory and Applications
Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency
ATS '09 Proceedings of the 2009 Asian Test Symposium
Signal and Power Integrity - Simplified
Signal and Power Integrity - Simplified
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
Minimization of crosstalk in high speed PCB
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Testing SoC interconnects for signal integrity using extended JTAG architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint-Driven Test Scheduling for NoC-Based Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Impact of crosstalk effects reduces the integrity of signals transmission on long interconnects which must be taken into consideration from the test point of view. Since use of ATE for at-speed test of crosstalk effects is very expensive, the BIST method is a proper method to perform such a test. In this paper, we propose a strategy in which all links among the switches of a regular 2-D NOC are tested in a fully parallel manner. The MVT patterns are generated by test pattern generators which are embedded in each of the switches and are applied to the links. To simultaneous test all links; the Quasi-synchronous method has been utilized for distributing of the clock across entire the NOC. In the proposed method not only test application time is reduced considerably, but also area overhead in overall NOC is reduced due to reuse of the first word of the output buffers of the switches for embedding the test pattern generators.