Design, Synthesis, and Test of Networks on Chips

Authors:
Partha Pratim Pande;Cristian Grecu;Andre Ivanov;Resve Saleh;Giovanni De Micheli
Affiliations:
Washington State University;University of British Columbia;University of British Columbia;University of British Columbia;Ecole Polytechnique Federale de Lausanne
Venue:
IEEE Design & Test
Year:
2005

Citing 13
Cited 24

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Abstract

For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This articlesurveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.