Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Scalable Parallel Computing: Technology,Architecture,Programming
Scalable Parallel Computing: Technology,Architecture,Programming
Computer
IEEE Micro
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Modelling and evaluation of a network on chip architecture using SDL
SDL'03 Proceedings of the 11th international conference on System design
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Designing a system on a chip with large number of cores poses many challenging problems. Designing a flexible on-chip communication network, which can provide the desired bandwidth and can be reused across many applications, is the key problem. In this chapter, we discuss how we can borrow and adapt the concept of packet switched communication from computer networks to design on-chip networks. In this new paradigm, the cores on the chip communicate among themselves by sending packets using a network of switches. We briefly describe the existing proposals, which have come up in the last couple of years. The network is built using a set of identical switches connected in regular topology. The important issues for design of the network are switch design, design of network access by cores and communication protocols. A particular protocol stack, called Nostrum, is described as a case study of protocols for on-chip communication. Ideas and tools can be borrowed from computer networks for evaluating on-chip networks.