Smart Memories: a modular reconfigurable architecture

  • Authors:

  • Ken Mai;Tim Paaske;Nuwan Jayasena;Ron Ho;William J. Dally;Mark Horowitz

  • Affiliations:

  • Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California

  • Venue:
  • Proceedings of the 27th annual international symposium on Computer architecture
  • Year:
  • 2000

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Abstract

Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular reconfigurable architecture called Smart Memories, targeted at computing needs in the 0.1&mgr; technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible applications, the memories, the wires, and the computational model can all be altered to match the applications. To show the applicability of this design, two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, are mapped onto the Smart Memories computing substrate. Simulations of the mappings show that the Smart Memories architecture can successfully map these architectures with only modest performance degradation.