METRO: a router architecture for high-performance, short-haul routing networks
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
A Router Architecture for Real-Time Communication in Multicomputer Networks
IEEE Transactions on Computers
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Stream communication between real-time tasks in a high-performance multiprocessor
Proceedings of the conference on Design, automation and test in Europe
Rent's rule based switching requirements
Proceedings of the 2001 international workshop on System-level interconnect prediction
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
System-level interconnect architecture exploration for custom memory organizations
Proceedings of the 14th international symposium on Systems synthesis
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Memory optimization in single chip network switch fabrics
Proceedings of the 39th annual Design Automation Conference
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Computer
Exploring the Design Space of Future CMPs
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
The Cost of Communication Protocols and Coordination Languages in Embedded Systems
COORDINATION '02 Proceedings of the 5th International Conference on Coordination Models and Languages
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
System Design: Traditional Concepts and New Paradigms
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Robust, High-Speed Network Design for Large-Scale Multiprocessing
Robust, High-Speed Network Design for Large-Scale Multiprocessing
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
The future of interconnection technology
IBM Journal of Research and Development
Beyond best effort: router architectures for the differentiated services of tomorrow's Internet
IEEE Communications Magazine
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System level interconnect design for network-on-chip using interconnect IPs
Proceedings of the 2003 international workshop on System-level interconnect prediction
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Embedded system design issues in ambient intelligence
Ambient intelligence
Interconnect intellectual property for network-on-chip (NoC)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal TDMA time slot and cycle length allocation for hard real-time systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Multi-processor system design with ESPAM
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Online resource management in a multiprocessor with a network-on-chip
Proceedings of the 2007 ACM symposium on Applied computing
Fitting the router characteristics in NoCs to meet QoS requirements
Proceedings of the 20th annual conference on Integrated circuits and systems design
pn: a tool for improved derivation of process networks
EURASIP Journal on Embedded Systems
NoC design flow for TDMA and QoS management in a GALS context
EURASIP Journal on Embedded Systems
Reducing Packet Dropping in a Bufferless NoC
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
System-scenario-based design of dynamic embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Microprocessors & Microsystems
Enabling dynamic and programmable QoS in SoCs
Proceedings of the Third International Workshop on Network on Chip Architectures
Temporal isolation on multiprocessing architectures
Proceedings of the 48th Design Automation Conference
Analysis and compute of real-time signal flow delay for network on-chip
Proceedings of the 2011 International Conference on Innovative Computing and Cloud Computing
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors
ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Microprocessors & Microsystems
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Users expect a predictable quality of service (QOS) of embedded systems, even for future, more dynamic, applications. System-on-chip designers use networks on chip (NOC) to solve deep submicron problems, and to divide global problems into local, decoupled problems. NOCs provide services through protocol stacks, and introducing guaranteed services enables IP re-use and platform-based design. It also provides globally predictable behaviour, as required by the user, when combining local, decoupled solutions. There are several levels of QOS commitment (correctness, completion, completion bounds), with increasing cost. A combination of guaranteed and best-effort (no commitment) services combines their respective attractive features: predictable behaviour, and good average resource utilisation. The ÆTHEREAL NOC is an example of this approach, and forms the basis of a QOS-based design style, as advocated in this chapter.