Integration, the VLSI Journal
Allocation of multiport memories for hierarchical data stream
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Architectural power optimization by bus splitting
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Minimizing the required memory bandwidth in VLSI system realizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
A Graph-Theoretic Approach for Register File Based Synthesis
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Guaranteeing On- and Off-Chip Communication in Embedded Systems
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Efficient general-purpose image compression with binary tree predictive coding
IEEE Transactions on Image Processing
Guaranteeing the quality of services in networks on chip
Networks on chip
Efficient exploration of on-chip bus architectures and memory allocation
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Multi-layer bus minimization for SoC
Journal of Systems and Software
Algorithmic techniques for memory energy reduction
WEA'03 Proceedings of the 2nd international conference on Experimental and efficient algorithms
Efficient exploration of bus-based system-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A learning-based approach to the automated design of MPSoC networks
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Selecting the optimal system: automated design of application-specific systems-on-chip
Proceedings of the 4th International Workshop on Network on Chip Architectures
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For data dominated applications, power consumption and memory bandwidth bottlenecks can be significantly alleviated with a custom memory organization. However, this potentially entails complex memory interconnections and a large routing overhead. This is undesirable for area cost, power consumption, and layout design complexity. By exploiting time-multiplexing opportunities over the long memory buses, this overhead can be significantly reduced. This paper proposes a system-level methodology for automated exploration of the interconnect architecture, which finds the optimal trade-off points for memory bus time-multiplexing. Experiments performed on real-life applications using our prototype tool show that even for very distributed memory organizations, the interconnect complexity can be significantly reduced to a cost-efficient, manageable level.