Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Communication estimation for hardware/software codesign
Proceedings of the 6th international workshop on Hardware/software codesign
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Architectural power optimization by bus splitting
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Generation of interconnect topologies for communication synthesis
Proceedings of the conference on Design, automation and test in Europe
System-level power/performance analysis for embedded systems design
Proceedings of the 38th annual Design Automation Conference
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
System-level interconnect architecture exploration for custom memory organizations
Proceedings of the 14th international symposium on Systems synthesis
An optimal memory allocation for application-specific multiprocessor system-on-chip
Proceedings of the 14th international symposium on Systems synthesis
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A hierarchical modeling framework for on-chip communication architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Model Refinement for Hardware-Software Codesign
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design space exploration for optimizing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
PeaCE: A hardware-software codesign environment for multimedia embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture exploration of NAND flash-based multimedia card
Proceedings of the conference on Design, automation and test in Europe
System-level bus-based communication architecture exploration using a pseudoparallel algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification
Journal of Signal Processing Systems
On-chip communication architecture exploration for processor-pool-based MPSoC
Proceedings of the Conference on Design, Automation and Test in Europe
A fast and effective dynamic trace-based method for analyzing architectural performance
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A parallel and distributed meta-heuristic framework based on partially ordered knowledge sharing
Journal of Parallel and Distributed Computing
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Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.