Architectural power optimization by bus splitting

System-level interconnect architecture exploration for custom memory organizations

Proceedings of the 14th international symposium on Systems synthesis

Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

The SegBus platform - architecture and communication mechanisms

Journal of Systems Architecture: the EUROMICRO Journal

Timing-aware power-optimal ordering of signals

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

Proceedings of the 46th Annual Design Automation Conference

Local search: is brute-force avoidable?

IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence

Topology/floorplan/pipeline co-design of cascaded crossbar bus

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect

Microelectronics Journal

Efficient exploration of bus-based system-on-chip architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph

Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design