Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Architectural power optimization by bus splitting
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper introduces a new coding scheme that simultaneously tackles different design issues of interconnections such as noise, crosstalk and power consumption. The scheme is based on temporal skewing between data words on even and odd lines of an interconnection link, and its hardware implementation is simple and area-efficient. The proposed scheme permits to double the bandwidth of the interconnect while improving its noise tolerance. This is achieved through the simultaneous use of two error detecting techniques: temporal redundancy and parity. Improved noise tolerance property provided by our design enables to decrease the power supply voltage and hence to reduce power consumption of the interconnect.