An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Guaranteeing the quality of services in networks on chip
Networks on chip
Energy-reliability trade-off for NoCs
Networks on chip
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A statistical model for estimating the effect of process variations on crosstalk noise
Proceedings of the 2004 international workshop on System level interconnect prediction
OCCN: a NoC modeling framework for design exploration
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Quality-of-service and error control techniques for network-on-chip architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Reliable communication in systems on chips
Proceedings of the 41st annual Design Automation Conference
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Enabling on-chip diversity through architectural communication design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 42nd annual Design Automation Conference
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Optimizing bus energy consumption of on-chip multiprocessors using frequent values
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Parallel, distributed and network-based processing
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Proceedings of the 41st annual Design Automation Conference
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Proceedings of the 43rd annual Design Automation Conference
Evaluation of SEU and crosstalk effects in network-on-chip switches
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Crosstalk- and SEU-Aware Networks on Chips
IEEE Design & Test
Arbiter synthesis approach for SoC multi-processor systems
Computers and Electrical Engineering
Fault-aware communication mapping for NoCs with guaranteed latency
International Journal of Parallel Programming
Journal of Electronic Testing: Theory and Applications
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Vicis: a reliable network for unreliable silicon
Proceedings of the 46th Annual Design Automation Conference
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems
Microelectronics Journal
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
A low-overhead and reliable switch architecture for Network-on-Chips
Integration, the VLSI Journal
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complement routing: A methodology to design reliable routing algorithm for Network on Chips
Microprocessors & Microsystems
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
Microelectronics Journal
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
An error-correcting unordered code and hardware support for robust asynchronous global communication
Proceedings of the Conference on Design, Automation and Test in Europe
OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimizing power and performance for reliable on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
Microprocessors & Microsystems
Analyzing the performance of mesh and fat-tree topologies for network on chip design
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Towards completely automatic decoder synthesis
Proceedings of the International Conference on Computer-Aided Design
Soft error mitigation in cache memories of embedded systems by means of a protected scheme
LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
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As technology scales toward deep submicron, on-chip interconnectsare becoming more and more sensitive to noisesources such as power supply noise, crosstalk, radiationinduced effects, etc. Transient delay and logic faults arelikely to reduce the reliability of data transfers across data-pathbus lines. This paper investigates how to deal withthese errors in an energy efficient way. We could opt forerror correction, which exhibits larger decoding overhead,or for the retransmission of the incorrectly received dataword. Provided the timing penalty associated with this lattertechnique can be tolerated, we show that retransmissionstrategies are more effective than correction ones from anenergy viewpoint, both for the larger detection capabilityand for the minor decoding complexity. The analysis wasperformed by implementing several variants of a Hammingcode in the VHDL model of a processor based on the SparcV8 architecture, and exploiting the characteristics of AMBAbus slave response cycles to carry out retransmissions in away fully compliant with this standard on-chip bus specification.