Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
A case for two-way skewed-associative caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Column-associative caches: a technique for reducing the miss rate of direct-mapped caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Area efficient architectures for information integrity in cache memories
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Reconfigurable caches and their application to media processing
Proceedings of the 27th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
A new cache architecture based on temporal and spatial locality
Journal of Systems Architecture: the EUROMICRO Journal
Essentials of Error-Control Coding Techniques
Essentials of Error-Control Coding Techniques
Performance Implications of Tolerating Cache Faults
IEEE Transactions on Computers
Predictive sequential associative cache
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs
PRDC '04 Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04)
Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Hierarchical Binary Set Partitioning in Cache Memories
The Journal of Supercomputing
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The size and speed of SRAM caches of embedded systems are increasing in response to demands for higher performance. However, the SRAM caches are vulnerable to soft errors originated from energetic nuclear particles or electrical sources. This paper proposes a new protected cache scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without compromising performance and area with respect to the similar one, fully associative cache. The results obtained from simulating some standard trace files reveal that the proposed scheme exhibits a performance near to fully associative cache but achieves a considerable fault detection coverage which is suitable to be used in the dependable computing.