ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors
IEEE Transactions on Computers
ACM Transactions on Computer Systems (TOCS)
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
ACM Computing Surveys (CSUR)
Architecture of a VLSI instruction cache for a RISC
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
On the Yield of VLSI Processors with On-Chip CPU Cache
IEEE Transactions on Computers
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A cache-defect-aware code placement algorithm for improving the performance of processors
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Microprocessors & Microsystems
RVC: a mechanism for time-analyzable real-time processors with faulty caches
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
A scalable circuit-architecture co-design to improve memory yield for high-performance processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
Soft error mitigation in cache memories of embedded systems by means of a protected scheme
LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
Hi-index | 14.98 |
The authors investigate how much cache miss ratios increase when blocks are disabled. It is shown how the mean miss ratio increase can be characterized as a function of the miss ratios of related caches, an efficient approach is developed for calculating the exact distribution of miss ratio increases from all fault patterns, and this approach is applied to the ATUM traces. Results reveal that the mean relative miss ratio increase from a few faults decreases with increasing cache size and is negligible (2% per defect) unless a set is completely disabled by faults. The maximum relative increase is also acceptable (5% per fault) if no set is entirely disabled.