Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors
IEEE Transactions on Computers
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Performance Implications of Tolerating Cache Faults
IEEE Transactions on Computers
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Itanium 2 Processor Microarchitecture
IEEE Micro
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
Performance of Graceful Degradation for Cache Faults
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to their small sizes, SRAMs are particularly vulnerable to parametric failures, resulting in significantly reduced yield. The underlying problem with SRAM is that there are conflicting requirements for read stability and writeability, such that optimizing the cell for read stability degrades its writeability. In this work, we present a circuit-architecture co-design technique that allows the decoupling of these conflicting requirements, resulting in significant yield enhancement at iso-area, while being scalable. Our technique is based on the observation that the write operation is not as performance critical as the read operation in high-performance microprocessors. Thus, the technique skews the cell design towards improving read stability at the circuit level at the expense of writeability. To handle the increased write failures in some dies, we apply simple architectural modifications that allow the write operation to take an additional cycle (stretched write cycle). By using our technique, we can improve yield from 37% to 69%, while having 3.4% performance impact on average, without increasing the size of the SRAM cell.