Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
On the inclusion properties for multi-level cache hierarchies
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ACM Computing Surveys (CSUR)
Architecture of a VLSI instruction cache for a RISC
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
On the Yield of VLSI Processors with On-Chip CPU Cache
IEEE Transactions on Computers
Performance Implications of Tolerating Cache Faults
IEEE Transactions on Computers
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A cache-defect-aware code placement algorithm for improving the performance of processors
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Selective wordline voltage boosting for caches to manage yield under process variations
Proceedings of the 46th Annual Design Automation Conference
Process variation aware SRAM/cache for aggressive voltage-frequency scaling
Proceedings of the Conference on Design, Automation and Test in Europe
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
RVC: a mechanism for time-analyzable real-time processors with faulty caches
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
A scalable circuit-architecture co-design to improve memory yield for high-performance processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Salvaging chips with caches beyond repair
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
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The authors study the tolerance of defects faults in cache memories. They argue that, even though the major components of a cache are linear RAMs (random-access memories), traditional techniques used for fault/defect tolerance in RAMs may be neither appropriate nor necessary for cache memories. They suggest a scheme that allows a cache to continue operation in the presence of defective/faulty blocks. Results are presented of an extensive trace-driven simulation analysis that evaluates the performance degradation of a cache due to defective blocks. From the results it is seen that the on-chip caches of VLSI processors can be organized so that the performance degradation due to a few defective blocks is negligible. The authors conclude that by tolerating such defects without a noticeable performance degradation, the yield of VLSI processors can be enhanced considerably.