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IEEE Transactions on Computers
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ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
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IEEE Transactions on Computers
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ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
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Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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ISPASS '11 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software
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SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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IOLTS '11 Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
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This paper presents a first-order analytical model for determining the performance degradation caused by permanently faulty cells in architectural and non-architectural arrays. We refer to this degradation as the performance vulnerability factor (PVF). The study assumes a future where cache blocks with faulty cells are disabled resulting in less cache capacity and extra misses while faulty predictor cells are still used but cause additional mispredictions. For a given program run, random probability of permanent cell failure, and processor configuration, the model can rapidly provide the expected PVF as well as lower and upper PVF probability distribution bounds for an individual array or array combination. The model is used to predict the PVF for the three predictors and the last level cache, used in this study, for a wide range of cell failure rates. The analysis reveals that for cell failure rate of up to 1.5e-6 the expected PVF is very small. For higher failure rates the expected PVF grows noticeably mostly due to the extra misses in the last level cache. The expected PVF of the predictors remains small even at high failure rates but the PVF distribution reveals cases of significant performance degradation with a non-negligible probability. These results suggest that designers of future processors can leverage trade-offs between PVF and reliability to sustain area, performance and energy scaling. The paper demonstrates this approach by exploring the implications of different cell size on yield and PVF.