Impact analysis of performance faults in modern microprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
On the Impact of Performance Faults in Modern Microprocessors
Journal of Electronic Testing: Theory and Applications
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We analyze the effect of errors in branch predictors, arepresentative example of speculative processor subsystems, tomotivate the necessity for fault tolerance in such subsystems. Wealso describe the design of fault tolerant branch predictors usinggeneral fault tolerance techniques. We then propose afault-tolerant implementation that utilizes the FiniteState Machine(FSM) structure of the Pattern History Table (PHT) and the set ofpotential faulty states to predict the branch direction, yetwithout strictly identifying the correct state. The proposedsolution provides virtually the same prediction accuracy as generalfault tolerant techniques, while significantly reducing theincurred hardware overhead.