On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology

Authors:
David Roberts;Nam Sung Kim;Trevor Mudge
Affiliations:
University of Michigan, Ann Arbor, MI 48109, United States;Intel Corporation, United States;University of Michigan, Ann Arbor, MI 48109, United States
Venue:
Microprocessors & Microsystems
Year:
2008

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Abstract

Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper, we are concentrating on one possible extension ...