A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities

Authors:
M. Nicolaidis;N. Achouri;L. Anghel
Affiliations:
-;-;-
Venue:
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2003

Citing 0
Cited 2

A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the architecture of a new memory Built-In Self-Repair approach targetingmemories affected by high defect densities (several orders of magnitude higher than in currenttechnologies). Such repair scheme is suitable for building memories in nano-technologies, which are subject to very high defect densities. The new approach allows combining two defected units to create a fault-free unit. For making this combination possible, the approach analyses the polarities of the errors produced by the faulty units of the memory, and combines units producing the same error polarities. The combination is done by means of functions that mask the errors of a particular polarity.