Analysis of Process Variation's Effect on SRAM's Read Stability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A low-power SRAM using bit-line charge-recycling technique
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Yield-driven near-threshold SRAM design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reliability-aware design for nanometer-scale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Preventing timing errors on register writes: mechanisms of detections and recoveries
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Process variation tolerant SRAM array for ultra low voltage applications
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Microprocessors & Microsystems
Thermal analysis of 8-T SRAM for nano-scaled technologies
Proceedings of the 13th international symposium on Low power electronics and design
Analyzing static and dynamic write margin for nanometer SRAMs
Proceedings of the 13th international symposium on Low power electronics and design
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM dynamic stability: theory, variability and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
ZerehCache: armoring cache architectures in high defect density technologies
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A variation-aware preferential design approach for memory based reconfigurable computing
Proceedings of the 2009 International Conference on Computer-Aided Design
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design
Variation tolerant 9T SRAM cell design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
An utilization driven framework for energy efficient caches
HiPC'08 Proceedings of the 15th international conference on High performance computing
Analysis of SRAM and eDRAM cache memories under spatial temperature variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Proceedings of the 47th Design Automation Conference
A holistic approach for statistical SRAM analysis
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Process variation aware SRAM/cache for aggressive voltage-frequency scaling
Proceedings of the Conference on Design, Automation and Test in Europe
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A discussion on SRAM circuit design trend in deeper nanometer-scale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable circuit-architecture co-design to improve memory yield for high-performance processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yield-driven near-threshold SRAM design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM write-ability improvement with transient negative bit-line voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power JPEG2000 encoder with iterative and fault tolerant error concealment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate estimation of SRAM dynamic stability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient cache design using variable-strength error-correcting codes
Proceedings of the 38th annual international symposium on Computer architecture
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Leakage-aware redundancy for reliable sub-threshold memories
Proceedings of the 48th Design Automation Conference
Realizing near-true voltage scaling in variation-sensitive l1 caches via fault buffers
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
MECCA: a robust low-overhead PUF using embedded memory array
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Analysis and optimization of SRAM robustness for double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Maximum-information storage system: concept, implementation and application
Proceedings of the International Conference on Computer-Aided Design
Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications
ACM Transactions on Embedded Computing Systems (TECS)
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
Integration, the VLSI Journal
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
Proceedings of the 49th Annual Design Automation Conference
Journal of Signal Processing Systems
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
Towards systematic roadmaps for networked systems
Proceedings of the 11th ACM Workshop on Hot Topics in Networks
Effects of process variation on the access time in SRAM cells
Euro-Par'12 Proceedings of the 18th international conference on Parallel processing workshops
AVICA: an access-time variation insensitive L1 cache architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN
Proceedings of the Conference on Design, Automation and Test in Europe
RESP: a robust physical unclonable function retrofitted into embedded SRAM array
Proceedings of the 50th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical SRAM read access yield improvement using negative capacitance circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques for compensating memory errors in JPEG2000
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single-ended, robust 8T SRAM cell for low-voltage operation
Microelectronics Journal
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip
Microprocessors & Microsystems
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology
Microelectronics Journal
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In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is proposed using the failure-probability and the yield-prediction models. The developed design strategy statistically sizes different transistors of the SRAM cell and optimizes the number of redundant columns to be used in the SRAM array, to minimize the failure probability of a memory chip under area and leakage constraints. The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.