IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Analyzing Soft Errors in Leakage Optimized SRAM Design
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Proceedings of the 42nd annual Design Automation Conference
Variation-tolerant circuits: circuit solutions and techniques
Proceedings of the 42nd annual Design Automation Conference
A Review of DASIE Code Family: Contribution to SEU/MBU Understanding
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Factors That Impact the Critical Charge of Memory Elements
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Variation Impact on SER of Combinational Circuits
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Soft-Error Vulnerability of Sub-100-nm Flip-Flops
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Terrestrial Neutron-Induced Soft Errors in Advanced Memory Devices
Terrestrial Neutron-Induced Soft Errors in Advanced Memory Devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical SRAM read access yield improvement using negative capacitance circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Submicrometer static random access memory cells are more susceptible to particle strike soft errors and increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, analytical models for the critical charge variations accounting for both die-to-die and within-die variations are proposed. The derived models are verified and compared to Monte Carlo simulations by using industrial 65-nm CMOS technology. This paper provides new design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability, especially, at lower supply voltages. It demonstrates that two extreme values of this coupling capacitor exist. The first value results in maximum relative variations and the other results in minimum relative variations. Therefore, the circuit designers can utilize these results to design the coupling capacitor to limit the variations under power and performance constraints in early design cycles. The derived analytical models account for the impact of the supply voltage and different particle strike conditions. These results are particularly important for soft error tolerant and variation tolerant designs in submicrometer technologies, especially, for low power operations.