Process variability-aware transient fault modeling and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On soft error rate analysis of scaled CMOS designs: a statistical perspective
Proceedings of the 2009 International Conference on Computer-Aided Design
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Increasing variability not only affects the behavior of contemporary ICs but also their vulnerability to transient error phenomenon especially radiation induced soft errors. Such variations in device parameters are caused by static process variations, dynamic variations in power supply and temperature and slow degradation of individual devices due to phenomena like Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). In this paper*, we analyze the impact of such variations on the Soft Error Rates (SER) of combinational logic circuits. Other contributions of this work also include tools that model threshold degradation of NMOS due to HCI and PMOS due to NBTI in logic circuits. Results were obtained for custom designed circuits and ISCAS-85 benchmarks. A detailed analysis of effect of threshold variations on SER is also presented with interesting observations.