IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Analyzing Soft Errors in Leakage Optimized SRAM Design
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 42nd annual Design Automation Conference
Variation-tolerant circuits: circuit solutions and techniques
Proceedings of the 42nd annual Design Automation Conference
A Review of DASIE Code Family: Contribution to SEU/MBU Understanding
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Factors That Impact the Critical Charge of Memory Elements
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Variation Impact on SER of Combinational Circuits
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Soft-Error Vulnerability of Sub-100-nm Flip-Flops
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Terrestrial Neutron-Induced Soft Errors in Advanced Memory Devices
Terrestrial Neutron-Induced Soft Errors in Advanced Memory Devices
IEEE Transactions on Signal Processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Sub-threshold SRAM cells are attractive because of their low leakage power and low access energy. However, the susceptibility of sub-threshold SRAM cells to soft errors is high due to their low supply voltage, high density, and shrinking geometry. Moreover, the increase in statistical variations in advanced nanometer CMOS technologies poses a major challenge for sub-threshold circuits designers. In this paper, analytical models for the sub-threshold SRAM critical charge variations, which account for both die-to-die (D2D) and within-die (WID) variations, are proposed. The derived models are then compared with Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper also provides novel design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. In addition, it demonstrates that the relative critical charge variability is minimum at a certain temperature value. Then, the circuit designer can employ these results with temperature control techniques to minimize the critical charge variability in the early design cycles, especially, for applications with strict soft error rate (SER) constraints. In addition, the proposed models show that the device sub-threshold swing coefficient can be optimized to minimize the relative critical charge variability.