Parameter variations and impact on circuits and microarchitecture

Authors:
Shekhar Borkar;Tanay Karnik;Siva Narendra;Jim Tschanz;Ali Keshavarzi;Vivek De
Affiliations:
Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR
Venue:
Proceedings of the 40th annual Design Automation Conference
Year:
2003

Citing 5
Cited 332

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Proceedings of the 16th Asia and South Pacific Design Automation Conference
Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power JPEG2000 encoder with iterative and fault tolerant error concealment

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Uncertainty-aware dynamic power management in partially observable domains

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Statistical lifetime reliability optimization considering joint effect of process variation and aging

Integration, the VLSI Journal
Analytical soft error models accounting for die-to-die and within-die variations in sub-threshold SRAM cells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling and resource binding algorithm considering timing variation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design-specific and thermally-aware methodology for trading-off power and performance in leakage-dominant CMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock-skew test module for exploring reliable clock-distribution under process and global voltage-temperature variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate estimation of SRAM dynamic stability

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance, energy efficiency, and scalability with GALS chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Autonomous multi-processor-SoC optimization with distributed learning classifier systems XCS

Proceedings of the 8th ACM international conference on Autonomic computing
A study on factors influencing power consumption in multithreaded and multicore CPUs

WSEAS Transactions on Computers
DEFCAM: A design and evaluation framework for defect-tolerant cache memories

ACM Transactions on Architecture and Code Optimization (TACO)
Re-synthesis for cost-efficient circuit-level timing speculation

Proceedings of the 48th Design Automation Conference
Hybrid modeling of non-stationary process variations

Proceedings of the 48th Design Automation Conference
Differential public physically unclonable functions: architecture and applications

Proceedings of the 48th Design Automation Conference
CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations

Proceedings of the 48th Design Automation Conference
Process variation-aware routing in NoC based multicores

Proceedings of the 48th Design Automation Conference
The evolution of standard cell libraries for future technology nodes

Genetic Programming and Evolvable Machines
Chip level statistical leakage power estimation using generalized extreme value distribution

PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Integrated circuit digital rights management techniques using physical level characterization

Proceedings of the 11th annual ACM workshop on Digital rights management
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processors

Computers and Electrical Engineering
A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory

Microelectronics Journal
Robust passive hardware metering

Proceedings of the International Conference on Computer-Aided Design
Scalable segmentation-based malicious circuitry detection and diagnosis

Proceedings of the International Conference on Computer-Aided Design
Active learning framework for post-silicon variation extraction and test cost reduction

Proceedings of the International Conference on Computer-Aided Design
On timing-independent false path identification

Proceedings of the International Conference on Computer-Aided Design
A lower bound computation method for evaluation of statistical design techniques

Proceedings of the International Conference on Computer-Aided Design
Accurate PTV, state, and ABB aware RTL blackbox modeling of subthreshold, gate, and PN-Junction leakage

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Dynamic management of thermally-induced clock skew: an implementation perspective

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection

Proceedings of the fifth ACM conference on Security and Privacy in Wireless and Mobile Networks
Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL

Proceedings of the great lakes symposium on VLSI
Statistical Timing and Power Optimization of Architecture and Device for FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints

ACM Transactions on Embedded Computing Systems (TECS)
On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks

ACM Transactions on Embedded Computing Systems (TECS)
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry

Proceedings of the 49th Annual Design Automation Conference
An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring

Proceedings of the 49th Annual Design Automation Conference
Dynamic clock stretching for variation compensation in VLSI circuit design

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

Journal of Signal Processing Systems
Power Modeling and Characterization of Computing Devices: A Survey

Foundations and Trends in Electronic Design Automation
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Computation of joint timing yield of sequential networks considering process variations

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A simple statistical timing analysis flow and its application to timing margin evaluation

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Exploiting input variations for energy reduction

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Cross-layer virtual observers for embedded multiprocessor system-on-chip (MPSoC)

Proceedings of the 11th International Workshop on Adaptive and Reflective Middleware
Tunable sensors for process-aware voltage scaling

Proceedings of the International Conference on Computer-Aided Design
On logic synthesis for timing speculation

Proceedings of the International Conference on Computer-Aided Design
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing

ACM Transactions on Architecture and Code Optimization (TACO)
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults

MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Adaptive reduction of the frequency search space for multi-vdd digital circuits

Proceedings of the Conference on Design, Automation and Test in Europe
Variation-tolerant OpenMP tasking on tightly-coupled processor clusters

Proceedings of the Conference on Design, Automation and Test in Europe
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging

Proceedings of the Conference on Design, Automation and Test in Europe
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

Proceedings of the 40th Annual International Symposium on Computer Architecture
Towards variation-aware system-level power estimation of DRAMs: an empirical approach

Proceedings of the 50th Annual Design Automation Conference
On testing timing-speculative circuits

Proceedings of the 50th Annual Design Automation Conference
Hardware/software approaches for reducing the process variation impact on instruction fetches

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
AppAdapt: opportunistic application adaptation in presence of hardware variation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level leakage variability mitigation for MPSoC platforms using body-bias islands

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip process variations compensation using an analog adaptive body bias (A-ABB)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable hardware trojan diagnosis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical SRAM read access yield improvement using negative capacitance circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VaMV: variability-aware memory virtualization

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Statistical thermal modeling and optimization considering leakage power variations

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Sliding-mode control to compensate PVT variations in dual core systems

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion

Journal of Electronic Testing: Theory and Applications
Static probabilistic worst case execution time estimation for architectures with faulty instruction caches

Proceedings of the 21st International conference on Real-Time Networks and Systems
Efficient statistical leakage analysis using deterministic cell leakage models

Microelectronics Journal
Embedded RAIDs-on-chip for bus-based chip-multiprocessors

ACM Transactions on Embedded Computing Systems (TECS)
Models for characterizing noise based PCMOS circuits

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Modeling the impact of permanent faults in caches

ACM Transactions on Architecture and Code Optimization (TACO)
Hardware acceleration of database operations

Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Fault detection and recovery efficiency co-optimization through compile-time analysis and runtime adaptation

Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs

Microelectronics Journal
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis

Proceedings of the International Conference on Computer-Aided Design
Static statistical MPSoC power optimization by variation-aware task and communication scheduling

Microprocessors & Microsystems
A column parity based fault detection mechanism for FIFO buffers

Integration, the VLSI Journal
Design configuration selection for hard-error reliable processors via statistical rules

Microprocessors & Microsystems
Amdahl's law in the era of process variation

International Journal of High Performance Systems Architecture

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Abstract

Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.