Supporting dynamic data structures on distributed-memory machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reconfigurable caches and their application to media processing
Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Fine-grain CAM-tag cache resizing using miss tags
Proceedings of the 2002 international symposium on Low power electronics and design
Design Challenges of Technology Scaling
IEEE Micro
Compiler-directed instruction cache leakage optimization
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Adaptive mode control: A static-power-efficient cache design
ACM Transactions on Embedded Computing Systems (TECS)
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
IATAC: a smart predictor to turn-off L2 cache lines
ACM Transactions on Architecture and Code Optimization (TACO)
Reducing data cache leakage energy using a compiler-based approach
ACM Transactions on Embedded Computing Systems (TECS)
Discovering and Exploiting Program Phases
IEEE Micro
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An energy efficient cache design using spin torque transfer (STT) RAM
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 49th Annual Design Automation Conference
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With the shift from scaling frequency to scaling the number of cores,efficiency becomes a primary design consideration. The ability to scale the numberof cores while pushing back the memory and power walls with small increasesin die size will require significant improvements in cache efficiencies.This paper provides strategies to improve L2/L3 data cache efficiencies by couplingvoltage scaling with flexible cache management policies. Specifically, wepropose a framework that encompasses i) off-line creation of a voltage-area profile,ii) on-line measurement of cache line utilization to drive voltage scaling,and, iii) changing the placement function to match the voltage-scaled area and theprogram-phase cache footprint. The proposed techniques were applied to severalbenchmarks resulting in performance efficiencies doubling, energy efficienciesimproving by 10% (relatively) with a 10% improvement in Energy Delay Product.