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MTDT '99 Proceedings of the 1999 IEEE International Workshop on Memory Technology, Design, and Testing
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ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
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ACM Transactions on Architecture and Code Optimization (TACO)
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ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
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HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
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HiPC'08 Proceedings of the 15th international conference on High performance computing
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GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
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ACM Computing Surveys (CSUR)
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Lower threshold voltages in deep submicron technologies cause more leakage current, increasing static power dissipation. This trend, combined with the trend of larger/more cache memories dominating die area, has prompted circuit designers to develop SRAM cells with low-leakage operating modes (e.g., sleep mode). Sleep mode reduces static power dissipation, but data stored in a sleeping cell is unreliable or lost. So, at the architecture level, there is interest in exploiting sleep mode to reduce static power dissipation while maintaining high performance.Current approaches dynamically control the operating mode of large groups of cache lines or even individual cache lines. However, the performance monitoring mechanism that controls the percentage of sleep-mode lines, and identifies particular lines for sleep mode, is somewhat arbitrary. There is no way to know what the performance could be with all cache lines active, so arbitrary miss rate targets are set (perhaps on a per-benchmark basis using profile information), and the control mechanism tracks these targets. We propose applying sleep mode only to the data store and not the tag store. By keeping the entire tag store active the hardware knows what the hypothetical miss rate would be if all data lines were active, and the actual miss rate can be made to precisely track it. Simulations show that an average of 73% of I-cache lines and 54% of D-cache lines are put in sleep mode with an average IPC impact of only 1.7%, for 64 KB caches.