A low power SRAM using auto-backgate-controlled MT-CMOS
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Reducing leakage in a high-performance deep-submicron instruction cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Frequent value locality and its applications
ACM Transactions on Embedded Computing Systems (TECS)
Energy efficient frequent value data cache design
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Adaptive mode control: A static-power-efficient cache design
ACM Transactions on Embedded Computing Systems (TECS)
Low Static-Power Frequent-Value Data Caches
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
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We propose a low-leakage cache architecture based on the observation of the spatio-temporal properties of data caches. In particular, we exploit the fact that during the program lifetime a few data values tend to exhibit both spatial and temporal locality in cache, i.e., values that are simultaneously stored by several lines at the same time. Leakage energy can be reduced by turning off those lines and storing these values in a smaller, separate memory. In this work we introduce an architecture that implements such a scheme, as well as an algorithm to detect these special values. We show that by using as few as four values we can achieve 18.45% leakage energy savings, with an additional 13.85% reduction of dynamic energy as a consequence of a reduced average cache access cost.