Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

Authors:
Michael Powell;Se-Hyun Yang;Babak Falsafi;Kaushik Roy;T. N. Vijaykumar
Affiliations:
School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

Citing 8
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Abstract

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across appli冒cations. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruc冒tion caches. We propose, gated-Vdd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-Vdd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.