Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design
Technologies for wireless computing
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A low power SRAM using auto-backgate-controlled MT-CMOS
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A system level memory power optimization technique using multiple supply and threshold voltages
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Design Challenges of Technology Scaling
IEEE Micro
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Minimizing power across multiple technology and design levels
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A static and dynamic energy reduction technique for I-cache and BTB in embedded processors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A leakage-energy-reduction technique for highly-associative caches in embedded systems
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Temperature-Dependent Optimization of Cache Leakage Power Dissipation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
STV-Cache: a leakage energy-efficient architecture for data caches
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A cache design for high performance embedded systems
Journal of Embedded Computing - Cache exploitation in embedded systems
A leakage-energy-reduction technique for cache memories in embedded processors
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An architectural level technique for a high performance and lowenergy cache memory is proposed in this paper.The key idea of our approach is to divide a cache memory into several number of cache blocks and to activate a fewparts of the cache blocks.The threshold voltage of each cache block is dynamically changed according to an utilization of each block.Frequently accessed cache blocks are woken up and others are put to sleep by controlling the threshold voltage.Since time overhead to change the threshold voltage can not be neglected,predicting a cache block which will be accessed in next cycle is important. History based prediction technique to predict cache blocks which should be woken up is also proposed.Experimental results demonstrated that the leakage energy dissipation in cache memories optimized by our approach can be less than 5%of energy dissipation in a cache memory which does not employ our approach.