Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
A low power SRAM using auto-backgate-controlled MT-CMOS
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A preactivating mechanism for a VT-CMOS cache using address prediction
Proceedings of the 2002 international symposium on Low power electronics and design
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
Design Challenges of Technology Scaling
IEEE Micro
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Static Energy Reduction Techniques for Microprocessor Caches
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Power Efficient Data Cache Designs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
A leakage-energy-reduction technique for highly-associative caches in embedded systems
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Understanding Scheduling Replay Schemes
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Hot-and-Cold: using criticality in the design of energy-efficient caches
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
| Hi-index | 0.00 |
Power consumption is becoming one of the most importantconstraints for microprocessor design in nanometer-scaletechnologies. Especially, as the transistor supply voltage andthreshold voltage are scaled down, leakage energy consumption isincreased even when the transistor is not switching. This paperproposes a simple technique to reduce the static energy due tosubthreshold leakage current. The key idea of our approach is toallow the ways within a cache to be accessed at different speedsand to place infrequently accessed data into the slow ways. We usedual-V_{t} technique to realize the non-uniform set-associativecache, and propose a simple replacement policy to reduce averageaccess latency. Experimental results on 32-way set-associativecaches demonstrate that any severe increase in clock cycles toexecute application programs is not observed and significant staticenergy reduction can be achieved, resulting in the improvement ofenergy-delay^{2} product.