Clustered voltage scaling technique for low-power design

An exact algorithm for low power library-specific gate re-sizing

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Energy minimization using multiple supply voltages

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

A low-power design method using multiple supply voltages

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

Datapath scheduling with multiple supply voltages and level converters

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

DAC '98 Proceedings of the 35th annual Design Automation Conference

Low-Power Divider

IEEE Transactions on Computers

Layout techniques supporting the use of dual supply voltages for cell-based designs

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Gate-level design exploiting dual supply voltages for power-driven applications

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

A completey on-chip voltage regulation technique for low power digital circuits

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Clock distribution using multiple voltages

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Provably good algorithm for low power consumption with dual supply voltages

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling (poster session)

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design

Power aware microarchitecture resource scaling

Proceedings of the conference on Design, automation and test in Europe

Low-power design methodology and applications utilizing dual supply voltages

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Power reduction by simultaneous voltage scaling and gate sizing

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Cell selection from technology libraries for minimizing power

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Future performance challenges in nanometer design

Proceedings of the 38th annual Design Automation Conference

Low-power technology mapping for mixed-swing logic

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Enhanced clustered voltage scaling for low power

Proceedings of the 12th ACM Great Lakes symposium on VLSI

On gate level power optimization using dual-supply voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Cell-based layout techniques supporting gate-level voltage scaling for low power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design

A low power scheduling scheme with resources operating at multiple voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Minimum-power retiming for dual-supply CMOS circuits

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

What is the limit of energy saving by dynamic voltage scaling?

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Microarchitecture-level power management

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low-power clock distribution using multiple voltages and reduced swings

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power: A First-Class Architectural Design Constraint

Computer

Power-Driven Challenges in Nanometer Design

IEEE Design & Test

Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Reducing Energy Consumption via Low-Cost Value Prediction

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Power efficiency of voltage scaling in multiple clock, multiple voltage cores

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Pushing ASIC performance in a power envelope

Proceedings of the 40th annual Design Automation Conference

Micro-architecture design and control speculation for energy reduction

Power aware computing

Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Applications

ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems

Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs

ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI

Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution

ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI

Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing

ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI

Level conversion for dual-supply systems

Proceedings of the 2003 international symposium on Low power electronics and design

Multivoltage scheduling with voltage-partitioned variable storage

Proceedings of the 2003 international symposium on Low power electronics and design

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Low-power technology mapping for FPGA architectures with dual supply voltages

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

A methodology for low power scheduling with resources operating at multiple voltages

Integration, the VLSI Journal

Level conversion for dual-supply systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment

Proceedings of the 41st annual Design Automation Conference

Enabling energy efficiency in via-patterned gate array devices

Proceedings of the 41st annual Design Automation Conference

Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

Proceedings of the 2004 international symposium on Low power electronics and design

Creating a power-aware structured ASIC

Proceedings of the 2004 international symposium on Low power electronics and design

Total power optimization through simultaneously multiple-vDD multiple-vTH assignment and device sizing with stack forcing

Proceedings of the 2004 international symposium on Low power electronics and design

A new algorithm for improved VDD assignment in low power dual VDD systems

Proceedings of the 2004 international symposium on Low power electronics and design

An approach for reducing dynamic power consumption in synchronous sequential digital designs

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Low-power dual Vth pseudo dual Vdd domino circuits

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

A leakage-energy-reduction technique for highly-associative caches in embedded systems

MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

High performance level conversion for dual VDD design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

On-chip power distribution grids with multiple supply voltages for high performance integrated circuits

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Increasing the energy efficiency of pipelined circuits via slack redistribution

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

A novel buffer circuit for energy efficient signaling in dual-VDD systems

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages

IEEE Transactions on Computers

On-chip digital power supply control for system-on-chip applications

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages

The Journal of Supercomputing

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Power distribution techniques for dual VDD circuits

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Minimizing total power by simultaneous Vdd/Vth assignment

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Low-power domino circuits using NMOS pull-up on off-critical paths

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Optimal module and voltage assignment for low-power

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Timing analysis in presence of supply voltage and temperature variations

Proceedings of the 2006 international symposium on Physical design

Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization

Proceedings of the 2006 international symposium on Physical design

Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

Optimal simultaneous module and multivoltage assignment for low power

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Optimality study of resource binding with multi-Vdds

Proceedings of the 43rd annual Design Automation Conference

Decoupling capacitors for multi-voltage power distribution systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A dual-VDD boosted pulsed bus technique for low power and low leakage operation

Proceedings of the 2006 international symposium on Low power electronics and design

Scheduling and optimal voltage selection with multiple supply voltages under resource constraints

Integration, the VLSI Journal

Voltage island aware floorplanning for power and timing optimization

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Digital Circuit Optimization via Geometric Programming

Operations Research

Temperature and voltage aware timing analysis: application to voltage drops

Proceedings of the conference on Design, automation and test in Europe

Low Power VLSI Design Techniques - The Current State

Integrated Computer-Aided Engineering

A provably good approximation algorithm for power optimization using multiple supply voltages

Proceedings of the 44th annual Design Automation Conference

FPGA Design Automation: A Survey

Foundations and Trends in Electronic Design Automation

Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Postplacement voltage assignment under performance constraints

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A leakage-energy-reduction technique for cache memories in embedded processors

Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications

A high-level clustering algorithm targeting dual Vdd FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A scalable algorithmic framework for row-based power-gating

Proceedings of the conference on Design, automation and test in Europe

On-chip power distribution grids with multiple supply voltages for high-performance integrated circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Optimal voltage assignment approach for low power using ILP

WSEAS Transactions on Circuits and Systems

Ultra Low Voltage High Speed Differential CMOS Inverter

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Network flow-based power optimization under timing constraints in MSV-driven floorplanning

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Evaluation of voltage interpolation to address process variations

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs

Proceedings of the 2009 international symposium on Physical design

Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Low-power FinFET circuit synthesis using multiple supply and threshold voltages

ACM Journal on Emerging Technologies in Computing Systems (JETC)

Optimal dual voltage assignment algorithm for low power under timing-constraints

ICC'08 Proceedings of the 12th WSEAS international conference on Circuits

A novel low-power full-adder cell for low voltage

Integration, the VLSI Journal

Incremental improvement of voltage assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Voltage-Island partitioning and floorplanning under timing constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Scheduling with multiple voltages

Integration, the VLSI Journal

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Journal of Signal Processing Systems

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Technology mapping and clustering for FPGA architectures with dual supply voltages

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Low power asynchronous circuit back-end design flow

Microelectronics Journal

Circuits and architectures for field programmable gate array with configurable supply voltage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A review of 0.18-µm full adder performances for tree structured arithmetic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Automating design of voltage interpolation to address process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Row-based power-gating: a novel sleep transistor insertion methodology for leakage power optimization in nanometer CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Inexact computing for ultra low-power nanometer digital circuit design

NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures

Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

Temperature aware datapath scheduling

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Differential static ultra low-voltage CMOS flip-flop for high speed applications

CSECS'11/MECHANICS'11 Proceedings of the 10th WSEAS international conference on Circuits, Systems, Electronics, Control & Signal Processing, and Proceedings of the 7th WSEAS international conference on Applied and Theoretical Mechanics

A routing architecture for FPGAs with Dual-VT switch box and logic clusters

ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications

Energy- and performance-aware scheduling of tasks on parallel and distributed systems

ACM Journal on Emerging Technologies in Computing Systems (JETC)

A Heuristic for reducing dynamic power dissipation in clocked sequential designs

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation

Variation-aware supply voltage assignment for simultaneous power and aging optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Inexact computing using probabilistic circuits: Ultra low-power digital processing

ACM Journal on Emerging Technologies in Computing Systems (JETC)