Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy minimization using multiple supply voltages
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Proceedings of the 2002 international symposium on Low power electronics and design
Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Voltage setup problem for embedded systems with multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
On improving the algorithmic robustness of a low-power FIR filter
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Hi-index | 0.00 |
This paper describes an adaptive power management architecture to reduce power consumption in digital filters. The proposed approach combines two low-power techniques which utilize supply voltage reduction. The first technique, multiple voltage distribution (MVD), attempts to reduce power consumption by assigning reduced supply voltages to circuit modules while satisfying timing constraints. The second technique, adaptive voltage scaling (AVS), dynamically adjusts these multiple voltages to meet throughput requirements resulting in further power reduction. An FIR filter application using the combined MVD-AVS power management scheme for two adaptively scaled supply voltages is shown to consume one-third the power of a fixed supply voltage scheme, and half the power consumed with a single supply AVS.