Optimal dual voltage assignment algorithm for low power under timing-constraints

Authors:
Yu-Cheng Lin;Cheng-Chiang Lin;Hsin-Hsiung Huang;Tsai-Ming Hsieh
Affiliations:
Dept. of Information and Electronic Commerce, Kainan University, Taoyuan, Taiwan;Dept. of Information and Computer Engineering, Chung Yuan Christian University, Chung-Li, Taiwan;Institute of Electronic Engineering, Chung Yuan Christian University, Chung-Li, Taiwan;Dept. of Information and Computer Engineering, Chung Yuan Christian University, Chung-Li, Taiwan
Venue:
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Year:
2008

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Abstract

In this paper, we present an optimal voltage assignment algorithm which assigns two supply voltages for each gate in the gate-level netlist. To the best of our knowledge, it is the first work to consider the impact of the level shifter using integer linear programming. The goal is to minimize the total power consumption under the delay constraints. First, we transform the gate-level netlist into a graph which the nodes and edges denote the gates and interconnect between gates, respectively. To speedup the runtime, the node-based concept is incorporated to reduce the timing constraints. All constraints, such as the delay constraints for each path and the total power constraints, are formulated as the linear programming. Hence, the voltage assignment is optimal. Experimental result shows that our proposed algorithm optimizes the power under timing constraints.