Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Proceedings of the 2003 international symposium on Low power electronics and design
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
Switching-activity driven gate sizing and Vth assignment for low power design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Register binding for clock period minimization
Proceedings of the 43rd annual Design Automation Conference
A Unified Optimal Voltage Selection Methodology for Low-Power Systems
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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In this paper, we present an optimal voltage assignment algorithm which assigns two supply voltages for each gate in the gate-level netlist. To the best of our knowledge, it is the first work to consider the impact of the level shifter using integer linear programming. The goal is to minimize the total power consumption under the delay constraints. First, we transform the gate-level netlist into a graph which the nodes and edges denote the gates and interconnect between gates, respectively. To speedup the runtime, the node-based concept is incorporated to reduce the timing constraints. All constraints, such as the delay constraints for each path and the total power constraints, are formulated as the linear programming. Hence, the voltage assignment is optimal. Experimental result shows that our proposed algorithm optimizes the power under timing constraints.