Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Placement with Alignment and Performance Constraints Using the B*-Tree Representation
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
Proceedings of the 42nd annual Design Automation Conference
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Timing-constrained and voltage-island-aware voltage assignment
Proceedings of the 43rd annual Design Automation Conference
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Post-placement voltage island generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Voltage Island Generation under Performance Requirement for SoC Designs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Optimal voltage assignment approach for low power using ILP
WSEAS Transactions on Circuits and Systems
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-voltage floorplan design with optimal voltage assignment
Proceedings of the 2009 international symposium on Physical design
Voltage-island driven floorplanning considering level-shifter positions
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Optimal dual voltage assignment algorithm for low power under timing-constraints
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Multicore parallel min-cost flow algorithm for CAD applications
Proceedings of the 46th Annual Design Automation Conference
Incremental improvement of voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A revisit to voltage partitioning problem
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Multicore parallelization of min-cost flow for CAD applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Low power discrete voltage assignment under clock skew scheduling
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Postplacement Voltage Island Generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-quality global routing for multiple dynamic supply voltage designs
Proceedings of the International Conference on Computer-Aided Design
Voltage island-driven power optimization for application specific network-on-chip design
Proceedings of the great lakes symposium on VLSI
Post-placement voltage island generation for timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
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Power optimization is a crucial concern for modern circuit designs. Multiple supply voltages (MSV's) provide an effective technique for the power optimization. This paper addresses the voltage-island generation problem for MSV designs at the post-floorplanning stage. We first present a general formulation of this problem that considers level-shifter planning and power-network routing resources. Without loss of solution quality, we propose an economical graph-based representation that needs only a linear number of nodes to the block number to model the block adjacency in a floorplan for the voltage-island generation. In contrast, previous works need a quadratic number of nodes. To tackle the addressed problem, we employ an ILP formulation which consists of (1) level-shifter aware wirelength estimation to capture the timing overhead, (2) voltage-island-clustering inequalities to avoid complicated constraint transformations, and (3) inequalities to capture the power-network routing-resource usage. Compared with previous works, our algorithm can produce better voltage islands in terms of power-network routing resources. Experimental results show that our algorithm can effectively reduce the power-network routing resource by up to 19.46% with a reasonable overhead of 4.03% more power consumption and using reasonable running time.