Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 37th Annual Design Automation Conference
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GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
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Proceedings of the 42nd annual Design Automation Conference
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RC delay metrics for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion with adaptive blockage avoidance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast dual-vdd buffering based on interconnect prediction and sampling
Proceedings of the 2007 international workshop on System level interconnect prediction
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations
Proceedings of the 2008 international symposium on Physical design
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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This paper presents the first in-depth study on applying dual VDD buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constraint. To tackle the problem of dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices, we develop a sampling-based sub-solutions (i.e. options) propagation method and a balanced search tree-based data structure for option pruning. We obtain 17x speedup with little loss of optimality compared to the exact option propagation. Moreover, compared to buffer insertion with single VDD buffers, dual-VDD buffers reduce power by 23% at the minimum delay specification. In addition, compared to the delay-optimal tree using single VDD buffers, our power-optimal buffered tree reduces power by 7% and 18% at the minimum delay specification when single VDD and dual VDD buffers are used respectively.