Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Performance-oriented technology mapping
Performance-oriented technology mapping
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient approach to simultaneous transistor and interconnect sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A performance-driven IC/MCM placement algorithm featuring explicit design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Interconnect layout optimization under higher-order RLC model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance driven global routing for standard cell design
Proceedings of the 1997 international symposium on Physical design
An efficient technique for device and interconnect optimization in deep submicron designs
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Buffer insertion for clock delay and skew minimization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
Performance optimization under rise and fall parameters
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Repeater block planning under simultaneous delay and transition time constraints
Proceedings of the conference on Design, automation and test in Europe
Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Provably good global buffering by multi-terminal multicommodity flow approximation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Memory-efficient interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Technology-based transformations
Logic Synthesis and Verification
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Layout-driven area-constrained timing optimization by net buffering
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An exact gate assignment algorithm for tree circuits under rise and fall delays
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On the signal bounding problem in timing analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
Proceedings of the 2003 international symposium on Physical design
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Layout-driven Timing Optimization by Generalized De Morgan Transform
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Power macromodeling of global interconnects considering practical repeater insertion
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Practical repeater insertion for low power: what repeater library do we need?
Proceedings of the 41st annual Design Automation Conference
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Tradeoff routing resource, runtime and quality in buffered routing
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
Proceedings of the 42nd annual Design Automation Conference
Efficient generation of short and fast repeater tree topologies
Proceedings of the 2006 international symposium on Physical design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
An efficient net ordering algorithm for buffer insertion
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Fast dual-vdd buffering based on interconnect prediction and sampling
Proceedings of the 2007 international workshop on System level interconnect prediction
Repeater insertion for concurrent setup and hold time violations with power-delay trade-off
Proceedings of the 2007 international symposium on Physical design
Layout-aware gate duplication and buffer insertion
Proceedings of the conference on Design, automation and test in Europe
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations
Proceedings of the 2008 international symposium on Physical design
Logic gates as repeaters (LGR) for area-efficient timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire synthesizable global routing for timing closure
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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We present efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion. Our algorithms are able to minimize dynamic power dissipation subject to given timing constraints. In addition, we compute the complete power-delay tradeoff curve for added flexibility. We extend our algorithm to take into account the effect of signal slew on buffer delay which can contribute substantially to overall delay. The effectiveness of these methods is demonstrated experimentally.