Performance-driven interconnect design based on distributed RC delay model

Simultaneous driver and wire sizing for performance and power optimization

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Rectilinear Steiner trees with minimum Elmore delay

DAC '94 Proceedings of the 31st annual Design Automation Conference

RC interconnect optimization under the Elmore delay model

DAC '94 Proceedings of the 31st annual Design Automation Conference

Minimal delay interconnect design using alphabetic trees

DAC '94 Proceedings of the 31st annual Design Automation Conference

Optimal equivalent circuits for interconnect delay calculations using moments

EURO-DAC '94 Proceedings of the conference on European design automation

Power distribution topology design

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

New performance-driven FPGA routing algorithms

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Optimal wire sizing and buffer insertion for low power and a generalized delay model

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Optimal wiresizing for interconnects with multiple sources

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Optimal wiresizing for interconnects with multiple sources

ACM Transactions on Design Automation of Electronic Systems (TODAES)

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

An efficient approach to simultaneous transistor and interconnect sizing

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Simultaneous buffer and wire sizing for performance and power optimization

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Optimal wiresizing under the distributed Elmore delay model

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Interconnect design for deep submicron ICs

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Delay bounded buffered tree construction for timing driven floorplanning

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Interconnect layout optimization under higher-order RLC model

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Performance driven global routing for standard cell design

Proceedings of the 1997 international symposium on Physical design

Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design

Proceedings of the 1997 international symposium on Physical design

Routing tree topology construction to meet interconnect timing constraints

ISPD '98 Proceedings of the 1998 international symposium on Physical design

A simultaneous routing tree construction and fanout optimization algorithm

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

MERLIN: semi-order-independent hierarchical buffered routing tree generation using local neighborhood search

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

A novel technique for sea of gates global routing

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

Routing tree construction under fixed buffer locations

Proceedings of the 37th Annual Design Automation Conference

The rectilinear Steiner arborescence problem is NP-complete

SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms

Is wire tapering worthwhile?

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

An interconnect topology optimization by a tree transformation

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Buffered Steiner trees for difficult instances

Proceedings of the 2001 international symposium on Physical design

Memory-efficient interconnect optimization

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

The power-pSteiner tree problem

Nordic Journal of Computing

Prediction of interconnect delay in logic synthesis

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Delay-related secondary objectives for rectilinear Steiner minimum trees

Discrete Applied Mathematics - The 1st cologne-twente workshop on graphs and combinatorial optimization (CTW 2001)

Minimum moment Steiner trees

SODA '04 Proceedings of the fifteenth annual ACM-SIAM symposium on Discrete algorithms

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Techniques for improved placement-coupled logic replication

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Design and verification of high-speed VLSI physical design

Journal of Computer Science and Technology

Maze routing steiner trees with effective critical sink optimization

Proceedings of the 2007 international symposium on Physical design

Layout-aware gate duplication and buffer insertion

Proceedings of the conference on Design, automation and test in Europe

Self-heating-aware optimal wire sizing under Elmore delay model

Proceedings of the conference on Design, automation and test in Europe

FPGA Design Automation: A Survey

Foundations and Trends in Electronic Design Automation

Thermal-aware Steiner routing for 3D stacked ICs

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Fast interconnect synthesis with layer assignment

Proceedings of the 2008 international symposium on Physical design

A polynomial time approximation scheme for timing constrained minimum cost layer assignment

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization

Proceedings of the 2009 international symposium on Physical design

A faster approximation scheme for timing driven minimum cost layer assignment

Proceedings of the 2009 international symposium on Physical design

Performance and thermal-aware Steiner routing for 3-D stacked ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Maze routing Steiner trees with delay versus wire length tradeoff

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power characteristics of inductive interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints

Proceedings of the 2014 on International symposium on physical design