Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
OTTER: optimal termination of transmission lines excluding radiation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact moment matching model of transmission lines and application to interconnect delay estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Constrained multivariable optimization of transmission lines with general topologies
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Near-optimal critical sink routing tree constructions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISPD '99 Proceedings of the 1999 international symposium on Physical design
FAR-DS: full-plane AWE routing with driver sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Hierarchical model order reduction for signal-integrity interconnect synthesis
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Studies the interconnect layout optimization problem under a higher-order RLC model to optimize not just the delay but also the waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wire-sizing optimization and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner (RATS) trees, providing a smooth trade-off among signal delay, waveform and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot and routing cost.