Hierarchical model order reduction for signal-integrity interconnect synthesis

Exact moment matching model of transmission lines and application to interconnect delay estimation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

PRIMA: passive reduced-order interconnect macromodeling algorithm

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Interconnect layout optimization under higher-order RLC model

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Buffer insertion for noise and delay optimization

DAC '98 Proceedings of the 35th annual Design Automation Conference

Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Efficient linear circuit analysis by Pade approximation via the Lanczos process

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems