A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
New efficient algorithms for computing effective capacitance
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
A practical repeater insertion method in high speed VLSI circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A repeater optimization methodology for deep sub-micron, high-performance processors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Methods for Calculating Coupling Noise in Early Design: A Comparative Analysis
ICCD '98 Proceedings of the International Conference on Computer Design
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Repeater block planning under simultaneous delay and transition time constraints
Proceedings of the conference on Design, automation and test in Europe
Hierarchical model order reduction for signal-integrity interconnect synthesis
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Memory-efficient interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
A sensitivity analysis of low-power repeater insertion
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the 42nd annual Design Automation Conference
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Making fast buffer insertion even faster via approximation techniques
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low-power repeater insertion with both delay and slew rate constraints
Proceedings of the 43rd annual Design Automation Conference
Repeater insertion for concurrent setup and hold time violations with power-delay trade-off
Proceedings of the 2007 international symposium on Physical design
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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