Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global interconnect sizing and spacing with consideration of coupling capacitance
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Efficient Crosstalk Estimation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Interconnect synthesis and planning for high-performance ic designs
Interconnect synthesis and planning for high-performance ic designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A decoupling method for analysis of coupled RLC interconnects
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Early probabilistic noise estimation for capacitively coupled interconnects
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Incremental delay change due to crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Efficient crosstalk noise modeling using aggressor and tree reductions
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Equivalent Waveform Propagation for Static Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Gate delay calculation considering the crosstalk capacitances
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An empirical study of crosstalk in VDSM technologies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Proceedings of the 42nd annual Design Automation Conference
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits
IEEE Design & Test
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A perturbation-aware noise convergence methodology for high frequency microprocessors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Crosstalk analysis in nanometer technologies
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Journal of Electronic Testing: Theory and Applications
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast bus waveform estimation at the presence of coupling noise
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A multiline model for time-efficient estimation of crosstalk
Analog Integrated Circuits and Signal Processing
Crosstalk pulsewidth calculation
Microelectronics Journal
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Smart non-default routing for clock power reduction
Proceedings of the 50th Annual Design Automation Conference
Silicon-aware distributed switch architecture for on-chip networks
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents a much improved, highly accurate yet efficient crosstalk noise model, the 2-pie model, and applies it to noise-constrained interconnect optimizations. Compared with previous crosstalk noise models of similar complexity, our 2-pie model takes into consideration many key parameters, such as coupling locations (near-driver or near-receiver), and the coarse distributed RC characteristics for victim net. Thus, it is very accurate (less than 6% error on average compared with HSPICE simulations). Moreover, our model provides simple closed-form expressions for both peak noise amplitude and noise width, so it is very useful for noise-aware layout optimizations. In particular, we demonstrate its effectiveness in two applications: (i) Optimization rule generation for noise reduction using various interconnect optimization techniques; (ii) Simultaneous wire spacing to multiple nets for noise constrained interconnect minimization.