Techniques for crosstalk avoidance in the physical design of high-performance digital systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimal reliable crosstalk-driven interconnect optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model
Proceedings of the conference on Design, automation and test in Europe
A postprocessing algorithm for crosstalk-driven wire perturbation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On integrating power and signal routing for shield count minimization in congested regions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a practical flow that automates the process of analyzing noise failures and determining and implementing the most appropriate design fixes in high performance designs. For each noise problem, the flow implicitly identifies the most sensitive relevant electrical parameter(s) which it then maps to a physical solution that minimizes design perturbation. Integrated with standard physical synthesis, it was used extensively in a high volume 90 nm multi-GHz microprocessor project.