An empirical study of crosstalk in VDSM technologies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A perturbation-aware noise convergence methodology for high frequency microprocessors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Crosstalk analysis in nanometer technologies
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
A multiline model for time-efficient estimation of crosstalk
Analog Integrated Circuits and Signal Processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single event crosstalk prediction in nanometer technologies
Analog Integrated Circuits and Signal Processing
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Noise estimation and avoidance are becoming critical,must have' capabilities in today's high performance IC design.An accurate yet efficient crosstalk noise model whichcontains as many driver/interconnect parameters as possible,is neccesary for any sensitivity based noise avoidanceapproach. In this paper, we present a complete analyticalcrosstalk noise model which incorporates all physical propertiesincluding victim and aggressor drivers, distributed RCcharacteristics of interconnects and coupling locations inboth victim and aggressor lines. We present closed-form analyticalexpressions for peak noise and noise width as wellas sensitivities to all model parameters. We then use thesemodel parameter sensitivities to analyze and evaluate variousnoise avoidance techniques such as driver sizing, wiresizing, wire spacing and layer assignment. Both our modeland noise avoidance evaluations are verified using realisticcircuits in 0:13µ technology. We also present effectiveness ofdiscussed noise avoidance techniques on a high performancemicroprocessor core.